Comments on: One Cerebras Wafer Beats An Exascale Super At Molecular Dynamics

By: Nibaba

Nibaba — Thu, 16 May 2024 22:46:15 +0000

Trash technology, they cannot power / cool well

By: Timothy Prickett Morgan

Timothy Prickett Morgan — Thu, 16 May 2024 20:50:54 +0000

In reply to John S. I think hollow will cool easier than pancakes. Nested donuts... mmmm.

By: Matt Dixon

Matt Dixon — Thu, 16 May 2024 16:27:13 +0000

Imagine stacking these like AMD does x3d or like HBM. Perhaps even a cache+interconnect logic layer between each WSE with vias through all layers that connect all of the interconnect wafers together like one big memory/cache controller.

By: Hunter

Hunter — Thu, 16 May 2024 15:22:53 +0000

Typo
Femtosecond
Not
Femptosecond

By: Antonio Romero

Antonio Romero — Thu, 16 May 2024 14:27:28 +0000

I don’t immediately know details about the supported scale and topologies but my understanding was that Tesla’s Dojo wafer scale compute engines leverage a TSMC waferscale. Interconnect to achieve roughly what you discuss here, at least for a single digit number of wafers. News stories around the Dojo launch cover this.

By: John S

John S — Thu, 16 May 2024 14:07:55 +0000

The trick with all these is power and cooling. And packaging. How small can we make cooling channels to remove heat, while at the same time bringing in power? Or so we also need to drop voltage? Where’s the next step below the 1.2V stuff I hear about? We’re slowly moving from 5V to 3.3V in hobbyist electronics, and I’m sure it’s lower elsewhere, but can we do some funky tricks where we give high voltage deep into the system, then drop it down efficiently and without much waste heat to then power just enough to make things work?

This is a total side step, but the comment on the 900 x 900 x 900 pancake stack made me think of the issues.

Heck, the torus (stovepipe style) could even have multiple layers torii stacked around each other. Hmm… maybe not, hard to get power/cooling in and out efficiently.

By: Timothy Prickett Morgan

Timothy Prickett Morgan — Thu, 16 May 2024 12:24:49 +0000

In reply to Calamity Jim. I like the toroid. You can put chocolate glaze on it, and then some sprinkles....

By: Calamity Jim

Calamity Jim — Thu, 16 May 2024 11:53:58 +0000

I remain quite partial to the Denny’s stack-of-pancakes approach to 3-D extension of the WSE computational dish-plates (with engineered heat-removal strategy). A 900-high stack (below the WSE-3 limit) would essentially provide for a 900x900x900 prism of cores, to efficiently simulate 700 million tantalum atoms, from which to evaluate pre-asymptotic behavior (eg. pre-Fickian property transport, of maple-syrup flavor) — that could be useful to parameterize related multicontinuum approximations (Kac/Goldstein?) (ref: https://www.nextplatform.com/2024/03/14/cerebras-goes-hyperscale-with-third-gen-waferscale-supercomputers/ )

But, of course, a stove-pipe approach, laid on its side, and curved to form a torus, could be the practical winner here (like a computational Tokamak, a perfect domain for Conway’s game of Life, and rather tasty in its interpretation as a donut). In any instance, great job by Cerebras, and the TriLabs MAD scientists (MoleculAr Dynamics), in demonstrating the substantial speedup of dataflow archs in such multi-Hamiltonian computation (if I understood well)!