I think you make a valid point. I have been calling it a data galaxy, not a data center.

Bob D stated “This history kind of forgets that one important step in there was AMD pasting an X86 front end on a RISC core and calling it the K5. About six years later they pasted in 64-bit registers and instructions into the more mature Athlon architecture (still RISC-cored) and entirely killed off the Itanium.”

Lets add some nuance here. The one important step … for market adoption and success …was when AMD extended the x86 instruction set from 32 to 64 bit. The AMD implementation enabled customers to easily migrate their existing 32 bit x86 code onto a 64 bit processor. AMD gave customers an easy migration path. This approach was exactly the same technical approach that DEC used to gently migrate customers from the 16 bit PDP-11 to the 32 bit VAX. PDP-11 code could run in compatibility mode on a VAX.

On the other hand Intel’s thought customers would move to the 64 bit Itanium, which required the labor intensive task of rewriting code for a different instruction set. Customers took the path of least resistance by adopting the AMD path forward. x86-64 was born.

Mel pullen says “IMHO, the internet and centralised cloud will be replaced by myriad mobile (and satallite) networks. Most of the Edge will communicate point to point.”

That is the vision I see and have been pondering on for several years.

The ARM move towards the data centre started around 2008-9. See https://ec.europa.eu/commission/presscorner/detail/en/IP_12_1014 which was when the project was coming to a close.

Acron RISC Machines was actually the name for ARM. It did ship a lot of chips and still does. Acorn Computer invented the architecture, but was just one of the customers.

So I think the article is correct.

I think the potential for ARM in the datacenter started to be more realistic 10 years ago when they introduced the 64-bit ARMv8, around 2011 (ARMv1 to ARMv7 were 32-bits). SPARC and others were already 64-bit since the mid 90s by comparison (15-to-20-year head-start). RISC-V is still quite young compared to those (and might want to channel Sophie Wilson’s neurons for upcoming iterations…).

I didn’t forget. I just used Intel as the example.