Could a microfluidic cooling channel solution be an option? We have applied this successfully in many different device applications.

I’d love to see 3-D stacking take-off in Cerebras-style WSE dataflow engines, at the dinner- or dessert-plate scale, a bit like a Denny’s or Waffle house stack of pancakes, with maple syrup (as “cooling” fluid). It could also help if we figured out some less-leaky transistors (possibly slightly exotic materials, with dielectric-whatnot). The lengths of signal lines through-the-stack would be shorter than going out horizontally to DIMM sockets, or extra accelerator wafers (or even normal chips), bringing another level of computational oomph to the 3-D device (a “tensor” processor). I second that motion!

You are correct of course. I did not read my own chart from the Meta Platforms story correctly.

A magical Peltier cooler? No. Liquid Vias? Yeah probably liquid immerse this sucka and pump fluid through little holes.

If the performance of 1 H100 is 1000 TFLOPS without considering sparsity then 500,000 H100s would be 500 Exaflops of FP16 performance or with Sparsity 1 Zettaflops.