Comments on: Deep Dive On Google’s Exascale TPUv4 AI Systems https://www.nextplatform.com/2022/10/11/deep-dive-on-googles-exascale-tpuv4-ai-systems/ In-depth coverage of high-end computing at large enterprises, supercomputing centers, hyperscale data centers, and public clouds. Sat, 22 Jun 2024 04:33:40 +0000 hourly 1 https://wordpress.org/?v=6.5.5 By: Wei Mai https://www.nextplatform.com/2022/10/11/deep-dive-on-googles-exascale-tpuv4-ai-systems/#comment-225868 Sat, 22 Jun 2024 04:33:40 +0000 https://www.nextplatform.com/?p=141335#comment-225868 The on chip SRAM size data of TPUv4 seems to wrong according there TPUv4 paper
“Like TPU v3, each TPU v4 contains two TensorCores (TC). Each TC contains four 128×128 Matrix Multiply Units (MXUs) and a Vector Processing Unit (VPU) with 128 lanes (16 ALUs per lane) and a 16 MiB Vector Memory (VMEM). The two TCs share a 128 MiB Common Memory
(CMEM).”
Total 160MB.

]]> By: Timothy Prickett Morgan https://www.nextplatform.com/2022/10/11/deep-dive-on-googles-exascale-tpuv4-ai-systems/#comment-207607 Sun, 23 Apr 2023 18:56:23 +0000 https://www.nextplatform.com/?p=141335#comment-207607 In reply to Adi.

Yeah, I am working on an analysis of that paper right now. Google could, I dunno, just answer questions when we ask them. It is supposed to be what the company does for a living (har har har).

]]> By: Adi https://www.nextplatform.com/2022/10/11/deep-dive-on-googles-exascale-tpuv4-ai-systems/#comment-207581 Sun, 23 Apr 2023 08:20:28 +0000 https://www.nextplatform.com/?p=141335#comment-207581 Hi, it seems that the recent TPUv4 paper that came out shows a surprising disparity between the numbers presented in the table.
https://arxiv.org/ftp/arxiv/papers/2304/2304.01433.pdf

I was pretty surprised to see that they were aiming for smaller die sizes (< 600mm2) and lower transistor count (22B) than all other competing designs in the 7nm category (typically 700-800mm2 with a 40-60B transistor count). I guess the targeting of a large "scale out" system (the 4K TPUv4s) made them put a greater emphasis on wires and interconnect than "scale up" compute ("beefier" systolic engines)?

]]> By: Peter C Salmon https://www.nextplatform.com/2022/10/11/deep-dive-on-googles-exascale-tpuv4-ai-systems/#comment-205658 Thu, 09 Mar 2023 18:18:08 +0000 https://www.nextplatform.com/?p=141335#comment-205658 For the tpu v4, does anyone know what the water flow rate is?
Or the physical size?

]]> By: Timothy Prickett Morgan https://www.nextplatform.com/2022/10/11/deep-dive-on-googles-exascale-tpuv4-ai-systems/#comment-199149 Wed, 12 Oct 2022 14:01:29 +0000 https://www.nextplatform.com/?p=141335#comment-199149 In reply to Hubert.

Not sure. Maybe the card is actually a lot smaller and there are 4X as many in a box?

]]> By: Fredrik https://www.nextplatform.com/2022/10/11/deep-dive-on-googles-exascale-tpuv4-ai-systems/#comment-199144 Wed, 12 Oct 2022 12:25:09 +0000 https://www.nextplatform.com/?p=141335#comment-199144 Thank you for sharing this interesting article around TPU

]]> By: Hubert https://www.nextplatform.com/2022/10/11/deep-dive-on-googles-exascale-tpuv4-ai-systems/#comment-199115 Tue, 11 Oct 2022 20:28:17 +0000 https://www.nextplatform.com/?p=141335#comment-199115 The TPUv4 liquid cooling (parallel feeds) looks more apt than v3 (series) and v2 (air). Could it be a hint of higher TDP than previous models?

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