Comments on: Pushing PCI-Express Switches And Retimers To Boost Server Bandwidth

By: Timothy Prickett Morgan

Timothy Prickett Morgan — Fri, 19 Apr 2024 14:32:54 +0000

In reply to RT. It's on my to-do list. . .

By: RT

RT — Fri, 19 Apr 2024 03:36:22 +0000

Any updates on that follow-up article with regards to the partnership with AMD and Broadcom on the AFL tech?

By: Rumi

Rumi — Thu, 28 Mar 2024 01:34:48 +0000

In reply to Timothy Prickett Morgan. Cool. We can do a sanity check in October again and I am sure they will have more to say, :-)

By: Timothy Prickett Morgan

Timothy Prickett Morgan — Wed, 27 Mar 2024 13:37:07 +0000

In reply to Rumi. Well, it has been a few weeks and things are changing fast. I would think that PCI-Express 6.0 would just about be cooked now so maybe they are just trying to accelerate PCI-Express 7.0 and get the cadence up. I would do the same thing for PCI-Express 8.0. There is more money to be made replacing Nvidia NVLink with a standard than selling a bunch of PCI peripherals, if they can pull this acceleration off.

By: Rumi

Rumi — Wed, 27 Mar 2024 12:14:55 +0000

PCIe 8.0 is up in the air! What we learned from BRCM during OCP2023 iS that THEY are pushing for expedition of PCIe 7.0 and roll out the prodouct portfolio along with it. My take is that PCIe 6.0 might be skipped, not 7.0. Thoughts?

By: Timothy Prickett Morgan

Timothy Prickett Morgan — Thu, 07 Mar 2024 14:19:42 +0000

In reply to Slim Albert. Me, too. Those optics, according to Jas, are inevitable by PCI-Express 8.0 because copper won't work after that. But, then again, people thought that would happen years ago. But after 100 Gb/sec signaling, we are going to hit some power issues and length of wire issues. It will be like two inches from the switch to the port is my guess, and that ain't gonna cut it. The optics are so much more expensive than copper that the latency add from retimers is well worth it. 6 nanoseconds is not so bad. It might make memory a bit jiggy jaggy, admittedly. But we can have fast HBM, slower local DRAM, and even slower CXL and have a memory hypervisor manage data placement across the complex and lie to the OS and apps about how much local memory it has and where. That's what I would do, anyway. Where's Charles Fan of MemVerge? Are you reading this Charles?

By: Slim Albert

Slim Albert — Thu, 07 Mar 2024 13:47:20 +0000

I can’t wait to see CPUs, GPUs, memory modules, and FPGAs, supporting PCIe 6.0 PAM-4, plugging into these Atlas 3 switches and Vantage 6 retimers, for the first realization of the CXL 3.0 cohesive integration protocol on real-world machines. The prospect of scaling coherency beyond multi-core CPU caches and into whole multi-cabinet heterogeneous systems, by design, and with low latency, is one that I find to be quite a game changer (especially from the rather commodity perspective of PCIe). It’ll probably take years to fully take advantage of the flexibility that this brings to datacenter and HPC/AI machinery, and so, the sooner it starts, the better (IMHO)! Co-Packaged Optics (CPO) might also reduce the need for local retimers I think (vs copper).