Comments on: Micron Revs Up Bandwidth And Capacity On HBM3 Stacks

By: Nicolas Dujarrier

Nicolas Dujarrier — Fri, 18 Aug 2023 18:35:28 +0000

I am also wondering how HBM memory stacks power consumption per bit in reading and writing compare to emerging non volatile memory MRAM like Everspin 1Gbit STT-MRAM or European research center IMEC VG-SOT-MRAM, and maybe future VCMA-MRAM ?

The goal would be to get a Non-Volatile Memory (NVM) HBM MRAM stack that is at the same time much, much lower power (at least 1000x) to current HBM stacks : it would be quite disruptive !!!

By: Nicolas Dujarrier

Nicolas Dujarrier — Fri, 18 Aug 2023 18:28:42 +0000

In reply to Slim Albert. I am wondering how HBM3 compare to LPDDR5x / LPDDR6 in terms of 1. Power consumption and 2. Cost (how many times more expensive it is at same capacity) ? The reason of that is, if HBM3 is much more power efficient, I am wondering why Apple is not attempting to use it in its Pro devices (Mac Pro, Macbook Pro, iPad Pro, iPhone Pro…) ?

By: ⟨φ|8^p|ψ⟩

⟨φ|8^p|ψ⟩ — Sat, 29 Jul 2023 17:47:16 +0000

In reply to Slim Albert. Pulled out me quantum computer to slice through the Salami figures ... HBM = 1.2 TB/s * 8 bit/B * 7 pJ/bit = 67 Watts. DDRx = 1.2 TB/s * 8 bit/B * 25 pJ/bit = 235 Watts.

By: Slim Albert

Slim Albert — Fri, 28 Jul 2023 00:28:33 +0000

In reply to dave. There's a ETH Zurich paper by Salami and others (2021, Power Consumption and Reliability of High-Bandwidth Memory) where they state 7 pJ/bit for HBM and 25 pJ/bit for DDRx. Theoretically then, you could transfer 3.5x as many bits per second through HBM and get the same power consumption as DDRx.

By: dave

dave — Thu, 27 Jul 2023 10:56:10 +0000

I have wondered for a while how many watts these things actually use. So if this single chiplet is running at a full speed of 1.2 TB/s how many watts does it consume?

By: Hubert

Hubert — Thu, 27 Jul 2023 03:45:14 +0000

HBM is so incredibly wide at 1024 bits of data per stack, and so 1 KB for eight stacks (mentioned in the article). In HBM3 it is split into four 32-bit pseudo-channels per die, so an 8-die stack has 32 of these pseudo channels, and an eight-stack group has 256. This suggests to me that HBM3 can read from 256 different sets of memory locations, over its 8-beat access sequence, getting 32 bytes from each, for further processing (maybe 128 locations for CPUs with 64-byte cache lines, vs GPU’s 32).

If that is correct, then it is quite awesome, and no wonder that memory is so expensive (and something for Micron to also produce). HBM2 had half the channels of HBM3, and HBM had half those of HBM2, so “random (sparse) access” perf should certainly increase with each gen (on top of raised clocks).