Comments on: Big Blue Can Still Catch The AI Wave If It Hurries

By: Timothy Prickett Morgan

Timothy Prickett Morgan — Mon, 04 Dec 2023 13:29:40 +0000

In reply to Lambert Schomaker. Thanks for clarifying. Appreciate it.

By: Lambert Schomaker

Lambert Schomaker — Mon, 04 Dec 2023 13:17:56 +0000

The “other chip” is a Xilinx Virtex FPGA, presumably hardware programmed for data streaming and PCI control. Although Northpole is ‘neuromorphic’, you will likely need a lot of the usual digital shuffling to get the ‘image’ cells filled, per core.

By: not hurrying

not hurrying — Tue, 14 Nov 2023 09:18:03 +0000

I thought everyone knew “IBM” and “hurries” do not belong in the same sentence.

By: HuMo

HuMo — Wed, 08 Nov 2023 02:33:12 +0000

In reply to Slim Jim. Hmmmm ... I smell a dish of recomposable disaggregated spaghetti monster calamari yumminess here! With trays of grilled CPUs linked to plates of "active memory" sauce, with plenty of CXL 3.0 optical fiber for throughput regularity! Think gastronomic cephalopods with an accurate deterministic left-brain that does math right, a lossy stochastic right-brain for tea and conversation, and a set of mesmerizingly luminescent pastafarian tentacles to bring it all together! A finest culinary of computational bliss! 8^b

By: Slim Jim

Slim Jim — Tue, 07 Nov 2023 01:24:49 +0000

Exactly! It’ll be interesting to see how this arch performs on decoder-oriented LLM processes and other GenAI which are the “hard” part of inference (eg. according to Cerebras’ Feldman in his HPCWire interview on the new Nvidia roadmap — that same roadmap which TNP pointfully questioned as well, and corrected!). A couple extra slightly “disheveled” Monday comments …

The two unknown-ish chips to the left of Northpole on the PCIe card (board photo) are, I believe, a Xilinx Virtex FPGA (silver-gray, large), and a Lattice FPGA (black, medium-size), likely used for I/O interfacing (markings somewhat visible by zooming and squinting!).

I wonder how broadly applicable “data-independent branching” (resulting in “deterministic control operation”) is, as a paradigm. It seems that parallelization is greatly eased where that independence arises (control flow graph only), but would exclude graph-traversal oriented processing (maybe CPUs are still best here? cf. Pingali et al., 2011. “The Tao of Parallelism in Algorithms”).

The multi-scale NoC is quite neat! (I might think of it as short-term and long-term memory loops … or not?).

The first sentence of the Conclusion to their Science paper is quite cool (IMHO) wrt perspective relativism: “As seen from the inside of the chip […] NorthPole appears as memory near compute; as seen from the outside of the chip […] it appears as an active memory.”. Wow!