A global system-replacement would demand:
$ A new software philosophy – but not as drop-dead as universally assumed;
$ PC-Efficient local (node) inter-processing – much more than just a block of PCs;
$ Massively-Parallel interconnects out of chips, modules, racks and warehouses – hierarchical software helps a lot there;
$ Internet-Efficient global processing – well, at least we’ve got that, though NOT as a uniform bottom-to-top-ology;
$ No worse aggregated power-dissipation – now there’s a thing, though the Great-and-Mighty reckon they can suffer the power-consumption itself;
$ Maybe hardest of all, how to seamlessly software-scale from local computational resource through to the whole global society (upwards and downwards), while recognising secured segments like a corporation or the US mainland;
$ Finally, how do I stop my minding YOUR business? This may be the opportunity to hardware-solve that thorny, data-burglary disaster. (Obviously, I really mean: how do I stop your minding MY own business, but I’m sure we all have this shared interest)

Intel hinted at ‘Exascale MPA FPGAs’, and that started out along the right lines, but there was no systems-level network-topology to go with it; they maybe have a their own broader view by now. Steve should be right – it makes sense – global networking IS the Next Platform. Is anyone out there heads-up on all this or only heads-down on the interconnect-spaghetti?

This all begs for a Systems view. Sure, good interconnects help though . . .

We have an entrenched model of what a server is, evolved and standardized from the IBM PC of 35 years ago, with a feedback loop which has hyper-optimized the components from which that model is deployed. CXL is an evolution of PCI in support of that model, normalizing and standardizing the asymmetric coherency of CCIX and CAPI, and providing an attach point to the CPU’s memory pipeline.

Various attempts to significantly cost-reduce (and back down on some diseconomies of scale in) the best practice server model have failed over the past 20 years. Generally these eliminate the I/O system of the best practice server, replacing it with a fabric connection through which other nodes, “real” networking, and storage are reached. This concept is not new: see IBM mainframe ESCON channels. But the application to improving price/performance of a large pool of servers never got market acceptance, as was intended by the original use of what became InfiniBand, some evolution of Xeon PHI for HPC around Omni-Path which never materialized, and microservers like AMD SeaMicro and HP/HPE Moonshot.

The CPU-centric model, which is a basic design assumption of PCI inherited by CXL, technically imposes the complexity of each CPU being the center of an autonomous world, and economically imposes a minimum node size to amortize the costs of the I/O system and other devices necessary to make that world autonomous.

I think it’s awesome that Intel is opening up its memory pipeline to outside devices via CXL. The gap is now one of symmetric vs asymmetric access, that is, the CPU centric model vs the network centric model.

The network-centric model (which Sun correctly articulated the vision for 40 years ago) allows a node to be as small as a DIMM, or more practically a single low-end CPU package with a few stacks of HBM and vertical flash mounted on that package. The CPU is a peripheral of the network. If Intel yielded to this model they’d be yielding most of the architectural control at the core of their business success in servers over the last 30 years.

I’m retired now (minus helping a particular startup); touched on the bus wars and had tiny impact on some of the survivors but had no major hand in any of the major winners of the past 30 years (yet); think that for hyperscale a network-centric model of much smaller nodes would carry a much lower CPU tax and be noticeably more cost effective than the local optimum which is today’s best practice; and think that enabling that network centric model requires not just what was done for the microservers which failed in the market because they did not fit in Cisco’s and Intel’s world of a decade ago, but also a rethreading of low level networking and addressing to connect user space software endpoints together regardless of location (ie a real solution to container networking…but containers and VMs aren’t needed in a world of bare metal microservers).

In terms of future concede or be left out.

In terms of past secondary market capital investment in Intel processor reuse will necessitate Intel opening its own CPU bus to independent development. Corrects that FTC v Intel Docket 9288 error regulating the closure of Intel’s CPU bus to Intel by disregarding competitive and complimentary participation on standards contribution.

Opening Intel x86 CPU bus whether Xeon or Core product is now a world wide industrial financial necessity. Preserves open market investment in Intel processors supporting new evolutionary system logic and board development by independent design producers. Makes by putting back to use, back in time Intel processors that are not obsolete for many ‘utility’ applications whether industrial or consumer.

Keeps the world at work and capitalism humming along.

Old CPUs can be salvaged with new independently designed that is evolutionary system logic (Northbridge/control hub) for new board production. World market compute needs are very different from the leading edge of platform innovation whether commercial or consumer.

Secondary x86 processor market on volume and value is today the primary market of exchange financing new procurements. Drives innovation for economic renewal across traditional design manufacturers and design producers including Intel.

Back nine year Core and Xeon CPU surplus alone not including their remaining system enclosures (multiply by x5) held as accumulated capital values by secondary ‘open market channels’ are valued by this analyst at Intel CPU 1K retail in excess $3.7 T, at Intel wholesale in excess of $1.2 T and CPU fire sale in excess of $300 B. These are conservative estimates based on Xeon v2/V3/v4 volume totaling 1.5 B units of supply presents a 15 year supply on today’s Scalable volume. Core easily adds another 2.7 B units of back nine years production volume.

Whether surplus CPU value or x5 and some might chose x3 system surplus value, its easy to see why secondary market holdings on their capital value are the primary financial enabler of new production on new procurements. Selling one results in the purchase of the other.

Intel will open the x86 CPU bus for back in time processor reuse because to refrain sends the world technical economy into a financial chaos by eliminating the primary source of funding today’s innovations on secondary market’s primary procurements.

Mike Bruzzone, Camp Marketing

No question, I had the PC Server on my mind when I was making my list. But clearly, every machine had its own bus, and nothing could plug into anything else, and small wonder that this business used to be so profitable.